• Mar 31, 2016 News!Vol.5, No.5 has been indexed by EI (Inspec).   [Click]
  • Aug 02, 2016 News!IJIEE Vol. 6, No. 4 issue has been published online! 10 papers which cover 3 specific areas are published in this issue.   [Click]
  • May 10, 2016 News!Papers published in Vol.6, No.3 have all received dois from Crossref.
General Information
Editor-in-chief

 
Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
" It is a great honor to serve as the editor-in-chief of IJIEE. I'll work together with the editorial team. Hopefully, IJIEE will be recognized among the readers in the related field."
IJIEE 2013 Vol.3(6): 567-52 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2013.V3.380

Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Shashikant Sharma, Anjan Kumar, Manisha Pattanaik, and Balwinder Raj
Abstract— As technology is continuously scaling down leakage current is increasing exponentially. Multi-Threshold CMOS technique is a well known way to reduce leakage current but it gives rise to a new problem i.e. ground bounce noise which reduces the reliability of the circuit and because of this circuit may incorrectly switch to the wrong value or may switch at the wrong time. Ground bouncing noise produced during sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of noise-aware forward body biased multimode MTCMOS circuit techniques to deal with the ground bouncing noise is evaluated in this paper. An additional wait mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by 93.28% and standby leakage current is reduced by 23.94% as compared to standard trimode MTCMOS technique.
To evaluate the significance of the proposed multimode Multi-Threshold CMOS technique, the simulation has been performed for 16-bit full adder circuit using BPTM 90nm standard CMOS technology at room temperature with supply voltage of 1V .

Index Terms— Forward body bias, ground bounce noise, leakage current, sleep to active mode transition.

The authors are with ABV-Indian Institute of Information Technology and Management, Morena Link Road, Gwalior 474010, Madhya Pradesh,India (e-mail: shashkant@gmail.com , dashyanjan@gmail.com, manishapattanaik @iiitm.ac. in, balwinder@iiitm.ac.in).

[PDF]

Cite: Shashikant Sharma, Anjan Kumar, Manisha Pattanaik, and Balwinder Raj, " Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders," International Journal of Information and Electronics Engineering vol. 3, no. 6, pp. 567-572, 2013.

Copyright © 2008-2016. International Journal of Information and Electronics Engineering. All rights reserved.
E-mail: ijiee@ejournal.net