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General Information
    • ISSN: 2010-3719
    • Frequency: Quarterly
    • DOI: 10.18178/IJIEE
    • Editor-in-Chief: Prof. Chandratilak De Silva Liyanage
    • Executive Editor: Jennifer Zeng
    • Abstracting/ Indexing : Google Scholar, Electronic Journals Library, Crossref and ProQuest, Ei (INSPEC, IET).
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Editor-in-chief

 
University of Brunei Darussalam, Brunei Darussalam   
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IJIEE 2014 Vol.4(2): 92-97 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2014.V4.415

Design and Optimization of CMOS 0.18μm Low Noise Amplifier for Wireless Applications

V. P. Bhale and U. D. Dalal
Abstract— A design and optimization of 3 GHz single ended Radio Frequency (RF) Low Noise Amplifier(LNA) for wireless applications using standard UMC 0.18μm CMOS technology is reported. Designing of RF circuit components is a challenging job, since even after performing lengthy calculations and finding parameter values it is less guarantee that the design performs as expected. In view of this the optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get the optimized starting values of components in the design. The obtained NSGA-II parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier achieves a power gain of 14.49 dB and a minimum Noise Figure of 1.897 dB is achieved. It dissipates 11.7 mW of power out of 1.8 V supply.

Index Terms— NSGA-II algorithm, LNA, noise figure, power gain.

The authors are with Electronics Engineering Department at S V National Institute of Technology, Surat 395 007, Gujarat, India (e-mail: v.bhale@rediffmail.com, udd@eced.svnit.ac.in).

[PDF]

Cite: V. P. Bhale and U. D. Dalal, " Design and Optimization of CMOS 0.18μm Low Noise Amplifier for Wireless Applications," International Journal of Information and Electronics Engineering vol. 4, no. 2, pp. 92-97, 2014.

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