• Jul 12, 2018 News!The submission for 2019 8th International Conference on Information and Electronics Engineering (ICIEE 2019) is officially open now !   [Click]
  • Aug 31, 2018 News!IJIEE Vol. 8, No. 3 issue has been published online!   [Click]
  • Aug 06, 2018 News!Vol.7, No.1-No.4 has been indexed by EI (Inspec).   [Click]
General Information
    • ISSN: 2010-3719
    • Frequency: Bimonthly
    • DOI: 10.18178/IJIEE
    • Editor-in-Chief: Prof. Chandratilak De Silva Liyanage
    • Associate Executive Editor: Ms. Jennifer Zeng
    • Executive Editor: Mr. Ron C. Wu
    • Abstracting/ Indexing : Google Scholar, Electronic Journals Library, Crossref and ProQuest, Ei (INSPEC, IET).
    • E-mail ijiee@ejournal.net

Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
" It is a great honor to serve as the editor-in-chief of IJIEE. I'll work together with the editorial team. Hopefully, IJIEE will be recognized among the readers in the related field."
IJIEE 2015 Vol.5(5): 361-365 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2015.V5.559

Design of a Modified Gabor Filter with Vedic Multipliers Using Verilog HDL

Naheean Rahim, Shamayla Islam, and Iqbalur R. Rokon
Abstract— Gabor Filters are widely used in all kinds of image processing. Gabor Filters include a memory, a controller and an arithmetic logic unit. The Gabor Filter designed in this project has a RAM type Memory, but a few changes were made in the Controller and the Arithmetic Logic Unit (ALU). The Arithmetic Logic Unit had a new type of multiplier called a Vedic Multiplier. So building a Gabor Filter with Vedic Multipliers is something that we have introduced in this paper. Using Vedic Multipliers, our filter was made faster without affecting the functionality of filter. The project included two phases where we did simulation of the Verilog Codes and synthesis of the whole Gabor Filter. For simulation and coding modules with Verilog HDL, we used ModelSim-Altera 6.5b (Quartus II 9.1) Starter Edition. For synthesis of the units and examining RTL schematic diagrams, we used Xilinx ISE 9.2i.

Index Terms— Gabor filter, MAC, vedic multipliers, verilog HDL, Xilinx.

Naheean Rahim and Shamayla Islam are with the Department of Electrical and Computer Engineering, North South University, Dhaka, Bangladesh (e-mail: naheean_rahim@yahoo.com, shamayla_91@hotmail.com).
Iqbalur Rahman Rokon is with North South University, Dhaka, Bangladesh. He was with VLSI Chip Research and Development (R&D), Emulex Corporation, California, USA (tel.: +88-01726246189; e-mail: irahman@northsouth.edu).


Cite: Naheean Rahim, Shamayla Islam, and Iqbalur R. Rokon, " Design of a Modified Gabor Filter with Vedic Multipliers Using Verilog HDL," International Journal of Information and Electronics Engineering vol. 5, no. 5, pp. 361-365, 2015.

Copyright © 2008-2018. International Journal of Information and Electronics Engineering. All rights reserved.
E-mail: ijiee@ejournal.net