—Program execution can be accelerated with efficient use of cache in real-time systems. And each program has its own instruction access pattern, which causes uneven distribution of accesses to the sets of instruction cache. In multi-core real-time systems, mapping tasks with similar instruction access patterns to the same core will incur massive conflicts and degrade the utilization of the cache. This paper proposes a cache-aware cooperative task mapping method to improve system efficiency in multi-core real-time systems. Our method quantifies the access frequency of instruction cache sets for each task, and then select tasks with complementary distributions to run on the same core, which can reduce inter-task interference and shorten the cache refill delay during context switch. Evaluation results show that the utilization of the system is improved by about 8.92% with the method.
—Cache, multi-core, real-time system, cooperative task mapping.
Endong Wang, Jicheng Chen, and Hongwei Wang are with the State Key Laboratory of High-end Server & Storage Technology Inspur (Beijing) Electronic Information Industry Co., Ltd, Beijing, 100085, China (e-mail: email@example.com, firstname.lastname@example.org, email@example.com).
Fan Ni and Yihan Li were with Beihang University, Beijing, 100191, China. They are now with the State Key Laboratory of High-end Server & Storage Technology Inspur (Beijing) Electronic Information Industry Co., Ltd, Beijing, 100085, China (e-mail: firstname.lastname@example.org, email@example.com).
Cite:Endong Wang, Fan Ni, Jicheng Chen, Hongwei Wang, and Yihan Li, "Cache-Aware Cooperative Task Mapping in Multi-core Real-Time Systems," International Journal of Information and Electronics Engineering vol. 6, no. 2, pp. 72-78, 2016.