• Jul 12, 2018 News!The submission for 2019 8th International Conference on Information and Electronics Engineering (ICIEE 2019) is officially open now !   [Click]
  • Aug 31, 2018 News!IJIEE Vol. 8, No. 3 issue has been published online!   [Click]
  • Aug 06, 2018 News!Vol.7, No.1-No.4 has been indexed by EI (Inspec).   [Click]
General Information
    • ISSN: 2010-3719
    • Frequency: Bimonthly
    • DOI: 10.18178/IJIEE
    • Editor-in-Chief: Prof. Chandratilak De Silva Liyanage
    • Associate Executive Editor: Ms. Jennifer Zeng
    • Executive Editor: Mr. Ron C. Wu
    • Abstracting/ Indexing : Google Scholar, Electronic Journals Library, Crossref and ProQuest, Ei (INSPEC, IET).
    • E-mail ijiee@ejournal.net

Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
" It is a great honor to serve as the editor-in-chief of IJIEE. I'll work together with the editorial team. Hopefully, IJIEE will be recognized among the readers in the related field."
IJIEE 2016 Vol.6(2): 79-83 ISSN: 2010-3719
DOI: 10.18178/IJIEE.2016.6.2.599

A New Hybrid 16-Bit16-Bit Multiplier Architecture by m:2 and m:3 Compressors

Shima Mehrabi, Reza Faghih Mirzaee, Sharareh Zamanzadeh, and Amirhossein Jamalian
Abstract—Compressors are mostly used in multipliers to reduce partial products in a parallel manner. Firstly, this paper draw a comparison between the conventional m:2 and m:3 compressors. Secondly, a new hybrid 16-bit16-bit multiplier is proposed in this paper with the aim of taking benefits from both kinds of compressors. The new design decreases the amount of carry signals by employing m:3 compressors in the first stage. It also accelerates reducing partial products by using m:2 compressors in the following stages. The second and third phases of multiplication are considered together in this paper. The synthesizable structural VHDL code is used to simulate and implement different architectures. Our investigations demonstrate that the new multiplier is the fastest one with reasonable power and area dissipations.

Index Terms—Compressor, m:2 compressor, m:3 compressor, full adder, half adder, hybrid architecture, multiplier, partial product reduction, ripple adder.

S. Mehrabi and R. Faghih Mirzaee are with the Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran (e-mail: sh.mehrabi@srbiau.ac.ir, r.f.mirzaee@qodsiau.ac.ir).
S. Zamanzadeh is with Physical Design (CAD) Laboratory, Shahid Beheshti University, G.C., Tehran, Iran (e-mail: sh_zamanzadeh@sbu.ac.ir).
A. Jamalian is with Artificial Intelligence, Faculty of Computer Science, Technical University of Chemnitz, Germany (e-mail: amj@hrz.tu-chemnitz.de).


Cite:Shima Mehrabi, Reza Faghih Mirzaee, Sharareh Zamanzadeh, and Amirhossein Jamalian, "A New Hybrid 16-Bit16-Bit Multiplier Architecture by m:2 and m:3 Compressors," International Journal of Information and Electronics Engineering vol. 6, no. 2, pp. 79-83, 2016.

Copyright © 2008-2018. International Journal of Information and Electronics Engineering. All rights reserved.
E-mail: ijiee@ejournal.net