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Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
" It is a great honor to serve as the editor-in-chief of IJIEE. I'll work together with the editorial team. Hopefully, IJIEE will be recognized among the readers in the related field."
IJIEE 2012 Vol.2(2): 151-155 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2012.V2.71

System Level Approach to NoC Design Space Exploration

R. K. Jena

Abstract—Network-on-Chip (NoC) has recently emerged as a communication solution for most of the System-on-Chip (SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, we proposed a PSO based integrated design space exploration framework for the NoC design at system level. The results show that our framework optimizes the design matrices like system throughput and average packet latency for the target application.

Index Terms—NoC, PSO, analytical model, design space exploration.

R. K. Jena is with the Institute of Management Technology, Nagpur, India (e-mail: rk_jena2@yahoo.com).


Cite: R. K. Jena, "System Level Approach to NoC Design Space Exploration," International Journal of Information and Electronics Engineering vol. 2, no. 2, pp. 151-155, 2012.

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