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Editor-in-chief

 
Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
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IJIEE 2012 Vol.2(2): 156-159 IS72SN: 2010-3719
DOI: 10.7763/IJIEE.2012.V2.72

Low Power Voltage Controlled Ring Oscillator Design with Substrate Biasing

Manoj Kumar, Sandeep K. Arya, and Sujata Pandey

Abstract—In the present work, improved designs for voltage controlled ring oscillators (VCO) with reverse body bias technique have been presented. In the proposed designs, output frequencies of VCOs have been controlled by varying the reverse bias voltage with improvement in power consumption. First VCO design with five inverter based delay cell shows frequency variation [1.3733-1.1218] GHz with varying NMOS substrate bias voltage from 0.0V to -1.5V. Second design with varying PMOS substrate bias from [1.8-3.3] V shows frequency variation of [1.3733-1.0009] GHz. Further, third design with joint substrate biasing of NMOS and PMOS transistors shows frequency variations [1.3251-0.81837] GHz. Power consumption has been reduced with reverse body bias in three proposed circuits Simulations have been performed by using SPICE based on TSMC 0.18µm CMOS technology. Power consumption of VCOs circuit has been compared with earlier reported circuits and proposed circuit’s shows better performance.

Index Terms—CMOS, low power, substrate bias and voltage controlled oscillator.

Manoj Kumar and Sandeep K. Arya are with the Department of Electronics and Communication Engineering, Guru Jambheshwar University of Science and Technology, Hisar, India (e-mail: manojtaleja@yahoo.com, arya1sandeep@rediffmail.com).
Sujata Pandey is with the Department of Electronics and Communication Engineering, Amity University, Noida, India (e-mail: spandey@amity.edu).

[PDF]

Cite: Manoj Kumar, Sandeep K. Arya, and Sujata Pandey, "Low Power Voltage Controlled Ring Oscillator Design with Substrate Biasing," International Journal of Information and Electronics Engineering vol. 2, no. 2, pp. 156-159, 2012.

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