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General Information
    • ISSN: 2010-3719
    • Frequency: Bimonthly
    • DOI: 10.18178/IJIEE
    • Editor-in-Chief: Prof. Chandratilak De Silva Liyanage
    • Associate Executive Editor: Ms. Jennifer Zeng
    • Executive Editor: Mr. Ron C. Wu
    • Abstracting/ Indexing : Google Scholar, Electronic Journals Library, Crossref and ProQuest, Ei (INSPEC, IET).
    • E-mail ijiee@ejournal.net

Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
" It is a great honor to serve as the editor-in-chief of IJIEE. I'll work together with the editorial team. Hopefully, IJIEE will be recognized among the readers in the related field."
IJIEE 2012 Vol.2(3): 366-368 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2012.V2.116

Semiconductor Die: Processing and Packaging

Satya Sai Srikant and Rajendra Prasad Mahapatra

Abstract—This paper presents the processes, steps and inspections, various testing stages involved starting from procurement of wafer onwards to individual Die form. Any semiconductor die or integrated circuit must performed all the processes of inspection and testing once it receives from any manufacturer and then it has to be procured to any Manufacturing Line for further process as a part of any Manufacturing products. This paper is also an attempt to isolate the entire good and bad Semiconductor Dies received from some Semiconductor Manufacturer at one place with complete package before going to Manufacturing Unit. It not only yields the efficiency of the Product in that Manufacturing line but also it saves a lot of manpower given for Failure Analysis, rework, retesting, etc and also it increases the Product reliability

Index Terms—Resonance, wafer, die, lapping, voids

The authors are with the SRM University, Modinagar, Delhi-NCR Campus (email: satya.srikant@gmail.com, mahapatra.rp@gmail.com)


Cite: Satya Sai Srikant and Rajendra Prasad Mahapatra, "Semiconductor Die: Processing and Packaging," International Journal of Information and Electronics Engineering vol. 2, no. 3, pp. 366-368, 2012.

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