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Editor-in-chief

 
Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
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IJIEE 2012 Vol.2(3): 369-373 ISSN: 2010-3719

The Performance Analysis of Fast DCT Algorithms on Parallel Cluster Architecture

Atri Sanyal and Swapan K Samaddar

Abstract—Clustered processor, having 16 clusters with 4 PE’s in each cluster and each PE having two ALU, which can perform simultaneously, is taken. The PE’s operate in a SIMD manner. The cluster and PE can transfer data from one another [1]. 4 FDCT algorithms: - namely i> Vetterli ii> Arai’s iii> Loeffler’s iv> Chen’s are taken into consideration. Our proposed 1D FDCT algorithm, parallel DCT is introduced. Examining all five algorithms using Timing Table it is concluded that percentage utilization is highest in Parallel DCT than other algorithms making it the most suitable to use in a parallel Cluster Architecture.

Index Terms—Cluster architecture, FDCT algorithm, JPEG, Parallel DCT, Timing Table.

A. Sanyal is with the NSHM College of Management and Technology, Kolkata, West Bengal, India (e-mail: atri.sanyal@nshm.com).
S. Samaddar is with School of Engineering, West Bengal University of Technology, Kolkata, and West Bengal, India (e-mail:swapansamaddar@gmail.com)

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Cite: Atri Sanyal and Swapan K Samaddar, "The Performance Analysis of Fast DCT Algorithms on Parallel Cluster Architecture," International Journal of Information and Electronics Engineering vol. 2, no. 3, pp. 369-373, 2012.

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