Abstract—A 1.3V, 11-bit, 6.5 MS/s Successive Approximation ADC is presented. The ADC operates with a differential peak to peak input of 1V. The ADC uses the common mode resetting triple level switching scheme, non-binary generalized redundant algorithm, a rail-to-rail latched comparator and a input bootstrapped sampling switch. The ADC was designed in 0.13um CMOS process. The simulation results of the ADC at an output data rate of 6.5 MS/s shows that it can achieve a signal-to-noise distortion ratio (SNDR) of 67.53 dB which corresponds to an Effective Number of Bits (ENOB) of 10.92. It also obtained a good linearity (DNL/INL) value of less than +-0.32LSB. The ADC consumes 414uW of power with a 1.3V supply resulting in a Figure of Merit (FOM) of 33fJ/conversion-step.
Index Terms—SAR ADC, triple level switching, non-binary, redundant algorithm.
Saisundar S, Simon Ng Sheung Yan, Huey Jen Lim, Bin Zhao, Dan Lei Yan and Minkyu Je are with Institute of Microelectronics, A*STAR(Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore CO 117685 (e-mail: sankas@ime.a-star.edu.sg).
Yoshida Akira is with CM Engineering Co. Ltd, 2-18-2 Nishi-Gotanda, Shinagawa-ku, Tokyo CO 141-0031, Japan (e-mail: yoshida.akira@cmengineering.co.jp).
Cite: Saisundar S, Simon Ng Sheung Yan, Huey Jen Lim, Bin Zhao, Dan Lei Yan, Minkyu Je, and Yoshida Akira, "11-Bit 6.5MS/s SAR ADC for Wireless Applications," International Journal of Information and Electronics Engineering vol. 2, no. 6, pp. 889-891, 2012.