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Editor-in-chief

 
Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
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IJIEE 2013 Vol.2(6): 944-947 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2012.V2.247

Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0.18μm CMOS Process

Raja Mohd. Noor Hafizi Raja Daud, Mamun Bin Ibne Reaz, and Labonnah Farzana Rahman

Abstract—A novel design of CMOS dynamic latch comparator with dual input single output with the differential amplifier stage is presented. The designed dynamic latch comparator is required for high-speed analog-to-digital converters to get faster signal conversion and to reduce the power dissipation, which is immune to noise than the previous works. In this paper, the design and analysis of a latch comparator using charge sharing circuit topology is illustrated to achieve low power and high-speed operation. The proposed circuit is designed using 0.18µm CMOS process. The simulated results shows that 100 MHz clock frequency with the power supply voltage (VDD) 3.3V and input range 3.3V produce the desired output signal. The topology of the proposed design is able to minimize the propagation delay and power consumption with the improved performances than other research works. Moreover, the different capacitor value and the transistor lengths produced the faster output, which is suitable for the successful operation of the ADC.

Index Terms—ADC, dynamic latch comparator, charge sharing, CMOS, low power, high speed.

Raja Mohd. Noor Hafizi Raja Daud is with the Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia. The authors are with the Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia. (e-mail: mamun.reaz@gmail.com).

[PDF]

Cite: Raja Mohd. Noor Hafizi Raja Daud, Mamun Bin Ibne Reaz, and Labonnah Farzana Rahman, "Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0.18μm CMOS Process," International Journal of Information and Electronics Engineering vol. 2, no. 6, pp. 944-947, 2012.

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