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General Information
    • ISSN: 2010-3719
    • Frequency: Quarterly
    • DOI: 10.18178/IJIEE
    • Editor-in-Chief: Prof. Chandratilak De Silva Liyanage
    • Executive Editor: Jennifer Zeng
    • Abstracting/ Indexing : Google Scholar, Electronic Journals Library, Crossref and ProQuest, Ei (INSPEC, IET).
    • E-mail ijiee@ejournal.net
Editor-in-chief

 
University of Brunei Darussalam, Brunei Darussalam   
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IJIEE 2013 Vol.2(6): 960-964 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2012.V2.250

Efficient Method of Power Management on System on Chip Communication Using Steiner Graph

K. Nirmaladevi and J. Sundararajan

Abstract—Power consumption become the major factors limiting the speed of very-large-scale integration (VLSI) circuits, while interconnect is becoming a primary power consumer. These factors bring new demands on the communication architecture of system-on-chips (SoCs). Current bus architectures such as AMBA, Core connect, and Avalon are convenient for designers but not efficient on power. This paper proposes a physical synthesis scheme for on-chip buses and bus matrices to minimize the power consumption, without changing the interface or arbitration protocols. By using a bus gating technique, data transactions can take shortest paths on chip, reducing the power consumption of bus wires to minimal. Experiments indicate that the gated bus from our synthesis flow can save more than 91% dynamic power on average data transactions in current AMBA bus systems, which is about 5–12% of total SoC power consumption, based on comparable amount of chip area and routing resources.

Index Terms—Bus gating, System on Chip, AMBA protocol.

K. Nirmaladevi is with the Department of ECE, Paavai Engineering College, Namakkal, Tamil Nadu, India (e-mail: nirmalnkl03@gmail.com).
J. Sundararajan is with the Pavai College of Technology, Tamil Nadu, India (e-mail: dharsini_71@yahoo.co.in).

[PDF]

Cite: K. Nirmaladevi and J. Sundararajan, "Efficient Method of Power Management on System on Chip Communication Using Steiner Graph," International Journal of Information and Electronics Engineering vol. 2, no. 6, pp. 960-964, 2012.

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