MODIFIED DUAL-CLCG METHOD AND ITS VLSI ARCHITECTURE FOR PSEUDORANDOM GENERATION

Authors

  • M. Tejeswar Kumar, Kamarushi Taraka Naga Manoj, Nalajala Sai Sravanthi, Nukavarapu Vamsi Krishna, Mannam Srikanth, Nagulapati Veeranji Author

DOI:

https://doi.org/10.48047/2mtb9y67

Keywords:

Pesudorandom Number Generator, Dual CLCG, Modified Dual CLCG, VLSI Architecture, FPGA Implementation, Verilog HDL, Parallel Processing, Random Sequence Generation, Digital Communication, Hardware Optimization, Low Power Design, High Throughput Systems.

Abstract

In modern digital communication and VLSI systems, the generation of high quality pseudorandom sequences plays a crucial role in 
ensuring data security, efficient encoding, and reliable transmission. This paper presents a Modified Dual Combined Linear Congruential Generator method along with its efficient VLSI architecture for pseudorandom number generation.

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Published

01.05.2026

Issue

Vol. 16 No. 2 (2026): volume 16 issue 2(2026)

Section

Articles

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How to Cite

MODIFIED DUAL-CLCG METHOD AND ITS VLSI ARCHITECTURE FOR PSEUDORANDOM GENERATION. (2026). International Journal of Information and Electronics Engineering, 16(2), 106-115. https://doi.org/10.48047/2mtb9y67