Performance-Driven Hybrid Approximate Multiplier Design with Selective Exact Computation for Embedded Systems
DOI:
https://doi.org/10.48047/w2cbw870Keywords:
Approximate computing, digital arithmetic, error compensation, low power design, multiplier architectureAbstract
Approximate computing has emerged as an efficient design methodology for achieving significant improvements in
power consumption, processing speed, and hardware utilization in error-tolerant applications such as convolutional neural networks, multimedia processing
Downloads
Download data is not yet available.
Downloads
Published
06.06.2026
Issue
Section
Articles
License
You are free to:
- Share — copy and redistribute the material in any medium or format for any purpose, even commercially.
- Adapt — remix, transform, and build upon the material for any purpose, even commercially.
- The licensor cannot revoke these freedoms as long as you follow the license terms.
Under the following terms:
- Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.
Notices:
You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation .
No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.
How to Cite
Performance-Driven Hybrid Approximate Multiplier Design with Selective Exact Computation for Embedded Systems . (2026). International Journal of Information and Electronics Engineering, 16(2), 482-489. https://doi.org/10.48047/w2cbw870
