Performance-Driven Design and Evaluation of Dynamic Comparators in Low-Power SAR ADCs
DOI:
https://doi.org/10.48047/40vn3r49Keywords:
Dynamic Comparator, SAR ADC, Low-Power Design, CMOS Technology, Propagation Delay, Noise Performance, Regenerative Latch, VLSI Design.Abstract
This paper presents a comprehensive analysis and classification of comparators used in low-power and low-data-rate Successive Approximation Register Analog-to-Digital Converters (SAR ADCs). Both voltage-domain and time-domain comparator architectures are investigated with respect to power consumption, comparison speed
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Published
06.06.2026
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How to Cite
Performance-Driven Design and Evaluation of Dynamic Comparators in Low-Power SAR ADCs. (2026). International Journal of Information and Electronics Engineering, 16(2), 490-495. https://doi.org/10.48047/40vn3r49
