An Optimized RISC Core Architecture Employing Vedic Mathematics for Low-Power Applications
DOI:
https://doi.org/10.48047/73t9w642Keywords:
Reduced Instruction Set Computer, Von-Neumann architecture, Verilog HDL, Vedic Mathematics, and Sutras.Abstract
This paper presents the design and implementation of a high-performance 16-bit Reduced Instruction Set Computer (RISC) processor incorporating a Vedic-based MultiplyAccumulate (MAC) unit, a hybrid Vedic–Karatsuba multiplier, and a parallel prefix adder architecture. The proposed design aims to enhance computational speed
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Published
06.06.2026
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How to Cite
An Optimized RISC Core Architecture Employing Vedic Mathematics for Low-Power Applications. (2026). International Journal of Information and Electronics Engineering, 16(2), 496-503. https://doi.org/10.48047/73t9w642
