Design of Halt-Mode and Monitoring-Mode On-Chip Debugger 2G for Core-A . International Journal of Information and Electronics Engineering, [S. l.], v. 3, n. 3, p. 324–328, 2013. Disponível em: https://www.ijiee.org/index.php/ijiee/article/view/691. Acesso em: 27 aug. 2026.