Design of Halt-Mode and Monitoring-Mode On-Chip Debugger 2G for Core-A
Keywords:
Debugger, JTAG, On-Chip Debugger, Processor.Abstract
Nowadays, the SoC is concentrated by all over the
world with interest. The design trend of the SoC is hardware
and software co-design which includes the design of hardware
structure in RTL level and the development of embedded
software. As the complexity of SoC design increases with
technology development, the observability of the SoC’s internal
state is no longer easy to achieve. Because of the above reasons,
debugging the SoC system becomes very difficult and
time-consuming. So we need a reliable debugger to find the bugs
in the SoC and embedded software. In this paper, we deal with
implementation of a hardware debugger named OCD2G which
is
based on IEEE 1149.1 JTAG standard and supports
halt-mode and monitoring-mode debugging. In order to verify
the operation of OCD2G, the designed debugger is integrated
into the 32bit RISC processor - Core-A (Core-A is an embedded
processor designed in South Korea) and is tested by
interconnecting with software debugger.
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