A 12Bit 200Msps Spilt-Based Pipeline ADC Design
Keywords:
OTA, pipeline ADC, split-based.Abstract
This paper presents a 12bit 200Msps pipeline ADC
fabricated in TSMC 0.18um CMOS technology. For high
resolution pipeline ADC design, the operation speed is limited by sampling capacitance load of OTA inside the ADC. The proposed ADC is realized in split-based pipeline architecture, sampling capacitance of ADC is separated into two channels. Each channel only has half capacitance, which reduce capacitive loading of OTAs in each channel and realize high speed operation of the ADC. The ADC achieves an SNDR of 64.7dB,
SFDR of 86.3dB with analog input frequency of 10MHz,
sampling frequency of 100MHz and differential amplitude of 1.25Vpp without digital calibration. The power dissipation of ADC is 356mW at 1.8V supply.
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