11-Bit 6.5MS/s SAR ADC for Wireless Applications

Authors

  • Saisundar. S, Simon Ng Sheung Yan, Huey Jen Lim, Bin Zhao, Dan Lei Yan, Minkyu Je, and Yoshida Akira Author

Keywords:

SAR ADC, triple level switching, non-binary, redundant algorithm.

Abstract

A 1.3V, 11-bit, 6.5 MS/s Successive Approximation ADC is presented. The ADC operates with a differential peak to peak input of 1V. The ADC uses the common mode resetting triple level switching scheme, non-binary generalized redundant algorithm, a rail-to-rail latched comparator and a input bootstrapped sampling switch. The ADC was designed in 0.13um CMOS process. The simulation results of the ADC at an output data rate of 6.5 MS/s shows that it can achieve a signal-to-noise distortion ratio (SNDR) of 67.53 dB which corresponds to an Effective Number of Bits (ENOB) of 10.92. It also obtained a good linearity (DNL/INL) value of less than +-0.32LSB. The ADC consumes 414uW of power with a 1.3V supply resulting in a Figure of Merit (FOM) of 33 fJ/conversion-step. 

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Published

01.12.2012

How to Cite

11-Bit 6.5MS/s SAR ADC for Wireless Applications . (2012). International Journal of Information and Electronics Engineering, 2(6), 889-891. http://www.ijiee.org/index.php/ijiee/article/view/499