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Editor-in-chief

 
Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
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IJIEE 2012 Vol.2(2): 185-188 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2012.V2.78

Multiplierless FIR Filter Implementation on FPGA

S. M. Badave and A. S. Bhalchandra

Abstract—Area complexity in the algorithm of finite impulse response (FIR) filter is mainly caused by multipliers. Among the multiplierless techniques of FIR filter, Distributed Arithmetic is most preferred area efficient technique. In this technique, precomputed values of inner product are stored in LUT, which are further added and shifted with number of iterations equal to the precision of input samples. But the exponential growth of LUT with the order of FIR filter, in its basic structure, makes it prohibitive for many applications. An improvement over the basic DA structure is presented in this paper, by the use of slicing of LUT to the desired length. An architecture of 16 tap FIR filter is presented, with different length of slice of LUT. Design implementation and synthesis result shown the improvement in speed of operation as well as saving in area, with more number of slices. Found drastic improvement in speed, when compared with earlier result.

Index Terms—FIR filter, multiplierless, distributed arithmetic.

S. M. Badave is with Dr. B. A. M. University, India (e-mail:smb.eed@gmail.com).
A. S. Bhalchandra is with the Department of Electronics and Telecommunication Engineering, Government College of Engineering, Aurangabad.

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Cite: S. M. Badave and A. S. Bhalchandra, "Multiplierless FIR Filter Implementation on FPGA," International Journal of Information and Electronics Engineering vol. 2, no. 2, pp. 185-188, 2012.

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