Abstract—Scaling is getting challenging with every technology node. Implant process requirements for defining conformal junctions in 3D device are very stringent. In addition, defining gate over topography is limited by lithography. Our solution to these problems is a novel junction-less FiNFET like transistor. Unlike conventional FiNFET the gate definition in this device is lithography independent. The fabricated NMOS and PMOS shows good transistor characteristics: ION =52.3uA/um, ION/IOFF ratio = 10 7, SS = 92mV/dec for NMOS and ION =15.4uA/um, ION/IOFF ratio = 10 5, SS = 90mV/dec for PMOS. We also show inverter VTC characteristics fabricated using this NMOS and PMOS.
Index Terms—CMOS, junctionless, independent gates
The authors are with Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), CO 117685 Singapore (e-mail: firstname.lastname@example.org).
Cite: A. Kamath, Z. X. Chen, N. Shen, X. Li, N. Singh, G. Q. Lo, and D.-L. Kwong, "Junctionless CMOS Transistors with Independent Double Gates," International Journal of Information and Electronics Engineering vol. 3, no. 1, pp. 13-15, 2013.