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Editor-in-chief

 
Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
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IJIEE 2011 Vol.1(1): 9-15 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2011.V1.2

Complete Circuit Level Random Variation Models of Nanoscale MOS Performance

Rawid Banchuin

Abstract—In this research, the complete analytical circuit level models of random variations in large and small signal parameters of any nanoscale MOS transistor have been proposed. Both triode and saturation regions have been explored. This research has been performed based upon the up to dated nanoscale regime MOS equations with the inclusion of all leading sources of variations instead of only threshold voltage variation. The proposed models have been verified at the nanometer level by using the Monte Carlo SPICE simulations and the Kolmogorov-Smirn of goodness of fit tests. These models are very accurate since they can fit the Monte Carlo based distribution with as high as 99% confidence. Obviously, they eliminate the gap between the circuit level and physical level design since the mismatches in the circuit level parameters can be now analytically formulated in terms of the physical level ones. So, the physical level causes and their relationships with the resulting circuit level mismatches can be revealed. Beside, the proposed models can also be expected to be the potential mathematical foundations for implementating the Electronic CAD cell libraries of the nanoscale MOS transistors. Hence, these models have been found to be efficient for the statistical/variability aware design of various CMOS analog/mixed signal circuits and systems in the nanoscale regime.

Index Terms—Nanoscale, CMOS, analog, mixed signal, circuit level, physical level, statistical design, variability aware design, circuit, system.

Rawid Banchuin is with the Department of Computer Engineering, Faculty of Engineering, Siam University, Bangkok, 10160 Thailand (e-mail: rawid_b@ yahoo.com).

[PDF]

Cite: Rawid Banchuin "Complete Circuit Level Random Variation Models of Nanoscale MOS Performance," International Journal of Information and Electronics Engineering vol. 1, no. 1, pp. 9-15, 2011.

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