Abstract—In this paper, an Efficient Very Large Scale Integration (VLSI) Architecture and Field Programmable Gate Array (FPGA) implementation of Adaptive Rank Order Filter (AROF) is proposed. AROF is a powerful technique for denoising an image corrupted by salt and pepper noise. The proposed method provides better filtering properties then it is possible with Adaptive Median Filter (AMF). The expansion of the window size in an AMF is based on whether the median is noisy or not. However, this criterion is not an appropriate when the noise density is moderate or high. Further the pixels processed by the AMF are reused in the AMF filtering process. The restored image using this scheme generally degrades the visual quality. The proposed method implements AROF in order to filter images with higher noise densities. The AROF uses median pixel or median computed from noise free pixels in order to replace noisy center pixel. The AROF adapts the window size itself when all pixels within the current window are noisy or when median itself is noisy. The AROF VLSI architectures developed is implemented on Xilinx Virtex XC2VP50-7ff1152 FPGA device. The pipelining and parallel processing techniques have been adapted in order to speed up the filtering process. The experimental results show that the proposed FPGA implementation of AROF has better performance then the AMF, when the noise density is moderate or high. The performance of the proposed algorithm is verified by applying Peak Signal to Noise Ratio (PSNR) and Image Enhance Factor (IEF).
Index Terms—Adaptive Median Filter, Adaptive Rank Order Filter, FPGA, Image Noise, Pipeline.
M. C Hanumantharaju is with the Department of Information Science and Engineering, Dayananda Sagar College of Engineering, Bangalore, India, Pin-560078 (corresponding author phone: +91-080-26662226; fax: 26660789; e-mail: mchanumantharaju@gmail.com).
M. Ravishankar, is with the Department of Information Science and Engineering, Dayananda Sagar College of Engineering, Bangalore, India, Pin-560078 (e-mail: ravishankarmcn@gmail.com).
D. R Rameshbabu, is with the Department of Computer Science and Engineering, Dayananda Sagar College of Engineering, Bangalore, India, Pin-560078 (e-mail: bobrammysore@gmail.com).
S. B Satish, is with the Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India, Pin-560078 (e-mail: satishbhairannawar@gmail.com).
[PDF]
Cite: M. C Hanumantharaju, M. Ravishankar, D. R Rameshbabu, and S. B Satish, "An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal,“ International Journal of Information and Electronics Engineering vol. 1, no. 1, pp. 94-98, 2011.
