• Jul 12, 2018 News!The submission for 2019 8th International Conference on Information and Electronics Engineering (ICIEE 2019) is officially open now !   [Click]
  • Aug 31, 2018 News!IJIEE Vol. 8, No. 3 issue has been published online!   [Click]
  • Aug 06, 2018 News!Vol.7, No.1-No.4 has been indexed by EI (Inspec).   [Click]
General Information
    • ISSN: 2010-3719
    • Frequency: Bimonthly
    • DOI: 10.18178/IJIEE
    • Editor-in-Chief: Prof. Chandratilak De Silva Liyanage
    • Associate Executive Editor: Ms. Jennifer Zeng
    • Executive Editor: Mr. Ron C. Wu
    • Abstracting/ Indexing : Google Scholar, Electronic Journals Library, Crossref and ProQuest, Ei (INSPEC, IET).
    • E-mail ijiee@ejournal.net

Faculty of Science, University of Brunei Darussalam, Brunei Darussalam   
" It is a great honor to serve as the editor-in-chief of IJIEE. I'll work together with the editorial team. Hopefully, IJIEE will be recognized among the readers in the related field."
IJIEE 2012 Vol.2(2): 269-273 ISSN: 2010-3719
DOI: 10.7763/IJIEE.2012.V2.96

BIST to Diagnosis Delay Fault in the LUT of Cluster Based FPGA

Nachiketa Das, Hafizur Rahaman, and Indrajit Banerjee

Abstract—This work reports a novel scheme for testing and diagnosis of a delay fault in LUT of a cluster based FPGA. The solution is based on implementing a BISTer structure to diagnosis the delay fault of the LUT. The BUT is implemented by chaining k-number of Look-Up Tables (LUT) in specific way. The ORA used a polling scheme to determine the most suitable result and an ATPG will generate the optimum test pattern that will have full test coverage. The entire scheme was implemented and simulated for Virtex-II FPGA .Here the intention was to overcome the drawbacks of previously used method. A design example using the proposed method shows better result. The entire testing scheme can also be applied in On-Line testing environment by using Xilinx Jbits 3.0 API (Application Program Interface) for Xilinx Virtex-II FPGAs.

Index Terms—Delay fault, FPGA, JBits, Look-up table (LUT), Testing.

The authors are with School of VLSI Technology, Bengal Engg. & Science University, Shibpur, India (e-mail: nachiketad@gmail.com, rahaman_h@it.becs.ac.in, e-mail: ibanerjee@it.becs.ac.in).


Cite: Nachiketa Das, Hafizur Rahaman, and Indrajit Banerjee, "BIST to Diagnosis Delay Fault in the LUT of Cluster Based FPGA," International Journal of Information and Electronics Engineering vol. 2, no. 2, pp. 269-273, 2012.

Copyright © 2008-2018. International Journal of Information and Electronics Engineering. All rights reserved.
E-mail: ijiee@ejournal.net